Nonvolatile memories (NVM) are classified into a stacked gate structure and a SONOS (silicon-oxide-nitride-oxide-silicon) gate structure depending on the type of its gate structure. The SONOS gate structure has gained increased interest due to the simplicity of the bitcell structure and process, low-voltage operation and its immunity to extrinsic charge loss as compared to traditional floating gate based nonvolatile memories. The SONOS gate structure nonvolatility is achieved by storing charge in nitride traps and surrounding the nitride with oxide to form an oxide-nitride-oxide stack on the sidewall of a gate electrode, also named a sidewall SONOS gate structure, which does not include a floating gate and is compatible with standard logic CMOS fabrication processes.
The sidewall SONOS gate structure typically utilizes thin and uniform tunnel oxide for both electron program and hole erase operations resulting in programming time slower than desired for many high-density embedded flash applications. Since the tunnel oxide is formed after the gate formation, the use of a thin bottom oxide grown on the silicon substrate for providing a thin tunnel oxide, however, also provides a thin sidewall oxide grown on the gate sidewall, which causes severe read disturb in the selected bitcell and gate disturb in the unselected bitcells sharing the same word line during a read operation. One approach to minimize gate disturb for the sidewall SONOS gate structure would be to increase the thickness of the tunnel oxide, but the use of the much thicker tunnel oxide will lower program/erase (P/E) speed. It is therefore desirable to provide a novel SONOS gate structure for inhibiting gate disturb and keeping high program/erase efficiency simultaneously.